The present invention relates to a semiconductor memory device including a bit line equalizer and sense amplifier drive line equalizer to precharge and equalize a bit line pair and sense amplifier line pair to predetermined potentials at an initial stage of a data access.
For example in the dynamic type semiconductor memory device, a bit line/word line short-circuiting defect, that is, a cross-fail defect, is liable to occur due to the microminiaturization and high integration density of elements. In order to improve a yield of the semiconductor devices, such defective bit lines and word lines are replaced by a repairing circuit (redundancy circuit) with corresponding spare bit lines and word lines. However, these defective bit lines and word lines are not electrically separated and, at a precharging time, that is, at an initial stage of a data access time, a bit line precharging voltage (for example, Vcc/2) and word line non-select voltage (for example, Vss=0V) are precharged onto these defective bit lines and word lines. For this reason, a short-circuiting current flows into the cross-fail area at the precharging time, thus resulting in an increase in a standby current at the precharging time.
In order to solve such a problem, a proposal has been made to provide a current limiter element between the bit line equalizer circuit and the bit line precharging power source line (for example, Vcc/2)--see the specification of U.S. patent application Ser. No. 5,499,211, Mar. 12, 1996.
FIG. 13 shows a portion of a circuit arrangement illustrated in the above U.S. Patent. In FIG. 13, a plurality of bit line pairs BL, bBL (bBL: a logically inverted version of BL) and plurality of word line WL (in FIG. 13, only one word line is shown) are shown in an intersecting relation.
In FIG. 13 are shown a bit line equalizer array comprised of a plurality of bit line equalizers 1 and a sense amplifier circuit array comprised of a plurality of sense amplifiers 2.
In the respective bit line equalizer, three N-channel MOS transistors Ql to Q3 are supplied at their gates with a bit line equalizer signal on a corresponding bit line equalizer control line 3. The MOS transistors Q1 to Q3 in the respective bit line equalizer circuit 1 are so controlled as to be turned ON at the precharging time, that is, at the initial stage of the data access time. By doing so, a potential on the bit line pair corresponding to the bit line equalizer 1 is set to a precharge voltage level (for example, Vcc/2). By doing so, it is possible to accomplish the precharging and equalizing of the voltage on the bit line pair.
Here, in the case where, at the precharging time, any cross-fail occurs between the precharging power source line 4 and the bit line equalizer array, a current limiter element 5 provided for this purpose serves to reduce a short-circuiting current from the bit line to the word line.
Further, the respective sense amplifier circuit 2 comprises a P-channel sense amplifier comprising two P-channel MOS transistors Q4, Q5 and an N-channel sense amplifier comprising two N-channel MOS transistors Q6, Q7. The sources of the P-channel MOS transistors Q4, Q5 are connected to a common junction which is connected to a P-channel sense amplifier drive signal 6 for driving the P-channel sense amplifier. Similarly, the sources of the N-channel MOS transistors Q6, Q7 are connected to a common junction which is connected to an N channel sense amplifier drive line 7.
A sense amplifier drive line equalizer 8 is connected to the sense amplifier drive lines 6 and 7. The sense amplifier drive line equalizer 8 comprises three N-channel MOS transistors Q8 to Q10 whose gates are controlled by an equalizing signal supplied to the sense amplifier drive line/equalizer control line. The MOS transistors Q8 to Q10 in the sense amplifier drive line equalizer 8 is so controlled as to be turned ON at the precharging time, that is, at the initial stage of the data access time. By doing so, a voltage on the sense amplifier drive line pair (6, 7) is set to a precharging voltage (for example, Vcc/2) on the precharging power source line 10. In this way, it is possible to accomplish the precharging and equalizing of the voltage on the sense amplifier drive line pair (6, 7).
Even when, however, such current limiter element 5 is provided, if any cross-fail occurs, a current flows through paths set out below at the precharging time.
(1) A charge on the bit line BL flows past the cross-fail portion (circle in FIG. 13) onto a word line WL set to a word line non-select voltage (Vss=0V) level (1 in FIG. 13).
(2) A current, flowing from the bit line BL at the path 1, flows past a turned-ON N-channel MOS transistor Ql in the bit line equalizer 1 and into the bit line BL from the bit line bBL as a pair relative to the bit line BL, so that potentials on the bit lines BL, bBL are lowered both to a near-Vss level (2 in FIG. 13).
(3) A charge for precharging the P-channel sense amplifier drive line 6 flows through the bit line BL after passing through the P-channel MOS transistor Q4 in the sense amplifier 2 (3 in FIG. 13).
(4) Through the N-channel MOS transistor Q9 in the sense amplifier drive line equalizer 8 a current flows from the precharging current source line 10 into the P-channel sense amplifier drive line (4 in FIG. 13).
Even in the DRAM semiconductor device of FIG. 13, a current flows from the precharging power source line 10 (precharging the P-channel sense amplifier drive line 6) into the word line WL through the sensor amplifier drive line equalizer 8, P-channel sense amplifier drive line 6, sense amplifier 2, bit line BL and cross-fail area, so that a standby current is increased at the precharging time.